Publication

Design and FPGA-implementation of a high performance timing recovery loop for broadband communications

Year

2009

Authors

  Javier Valls Coquillat

Co-authors

V. Torres, A. Perez-Pascual, T. Sansaloni, J.Valls

Journal

Journal of Signal Processing Systems

Volume

56

Number

1

Pages

17-23

Dates

Julio

DOI

  http://dx.doi.org/10.1007/s11265-008-0252-0

Research Groups

Digital Systems Integration Group (GISED)