Javier Valls Coquillat – ITEAM

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ITEAM UPV

Outstanding Triumph at IMS 2023!

José Capmany’s Nu-MESH Project at PRL-iTEAM Secures Funding from the European Research Council (ERC) in the #ERCPoC 2023 Competition

Jaime Sanchez awarded by the European Broadcasting Union (EBU)

Are We Facing the End of 20th Century Mobility?

iTEAM 2022 Scientific Production List

The Tender Announcement for Phase 3 of the Advancing-5G-Immersive project has been published

The Tender Announcement for Phase 3 of the Advancing-5G-Digital-Twins project has been published

5G research will lead to more developed 6G technology

Interview with José Capmany Francoy

The ‘Metalized RF filters for satellites’ research led by Carmen Bachiller, finalist for the TCT Awards 2023

Profile

Javier Valls Coquillat


Position	FACULTY & VISITING PROFESSOR - Associate Professor
Email	jvalls@eln.upv.es
Phone	34 96 284 9418
Groups	Digital Systems Integration Group (GISED)
Bio Research Works	Bio Javier Valls received the telecommunication engineering degree from the Universidad Politecnica de Cataluna, Spain, and the Ph.D. degree in telecommunication engineering from the Universidad Politecnica de Valencia, Spain, in 1993 and 1999, respectively. He is with the Department of Electronics at Universidad Politecnica de Valencia, Valencia, Spain, since 1993, where he currently is an Associate Professor. His current research interests include the design of FPGA-based systems, computer arithmetic, VLSI signal processing, and digital communications. Research Works 2016 Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm 2015 Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes Reduction of complexity for Non-binary LDPC decoders with compressed messages Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser High-performance NB-LDPC decoder with reduction of message exchange 2014 Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes with Low Error-Floor Non-Binary LDPC Decoder based on Symbol Flipping with Multiple Votes Multiple-Vote Symbol-Flipping Decoder for Non-Binary LDPC Codes Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree Non-Binary LDPC Decoder Based on Simplified Enhanced Generalized Bit Flipping Algorithm 2013 Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes 2012 Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes Serial Symbol-Reliability Based Algorithm For Decoding Non-Binary LDPC Codes Hardware Architecture of a Gaussian Noise Generator Based on Inversion Method Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm High-Throughput FPGA-based Emulator for Structured LDPC Codes Fully-parallel LUT-based (2048,1723) LDPC Code Decoder for FPGA 2011 Low cost Hardware Implementation of logarithm approximation High speed RS(255,239) decoder based on LCC decoding 2010 FPGA implementation of atan(Y/X) based on Logarithmic transformation and LUT-based techniques 2009 FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic Design and FPGA-implementation of a high performance timing recovery loop for broadband communications Low-power FPGA-implementation of atan(Y/X) using Look-Up Table methods for communication applications Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems Power consumption reduction in a Viterbi Decoder for OFDM-WLAN 50 Years of CORDIC: Algorithms, Architectures and Applications 2008 Efficient mapping of CORDIC Algorithm for OFDM-based WLAN 2007 Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN Time synchronization for the IEEE 802.11a/g WLAN Standard Improvement of a Time Synchronization Algorithm for IEEE 802.11a/G WLAN Standard Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs 2006 Design of high performance timing recovery loops for communication applications 2005 Statical power estimation for FPGAs Efficient pipeline FFT processors for WLAN MIMO-OFDM systems Efficient FPGA implementation of CORDIC algorithm for circular and linear coordinates Efficient mapping on FPGA of a Viterbi decoder for wireless LANs 2003 Area-efficient FPGA-based FFT processor Efficient FPGA-Implementation of two's complement digit-serial/parallel multipliers Area-Optimized Implementation of Quadrature Direct Digital Frequency Synthesizers on LUT-based FPGAs Digit-serial Complex-Number Multipliers on FPGAs 2002 Evaluation of CORDIC Algorithms for FPGA design 2001 Optimisation of direct digital frequency synthesizers based on CORDIC

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Outstanding Triumph at IMS 2023!

31 July, 2023 By Pau Arce Vila
José Capmany’s Nu-MESH Project at PRL-iTEAM Secures Funding from the European Research Council (ERC) in the #ERCPoC 2023 Competition

31 July, 2023 By Pau Arce Vila
Jaime Sanchez awarded by the European Broadcasting Union (EBU)

19 June, 2023 By Pau Arce Vila
Are We Facing the End of 20th Century Mobility?

18 June, 2023 By Pau Arce Vila
iTEAM 2022 Scientific Production List

14 June, 2023 By Alicia María Abad García

PRL researchers develop optical sensors embedded in mattresses to detect sleep apnea

18 April, 2018 By Ivana Gasulla Mestre
New antenna for SOTM applications successfully developed.

21 December, 2016 By a3p
Daniel Pérez receives the COIT best Spanish PhD thesis award

6 June, 2018 By Ivana Gasulla Mestre
Ivana Gasulla has been granted a Consolidator Grant from the European Research Council

4 January, 2017 By a3p
Inventing the future of photonic integration

27 January, 2020 By Ivana Gasulla Mestre

The Ministry of Science and Innovation grants to ITEAM the project “Optimum Planning of LTE Frequencies”

22 April, 2010 By a3p
CALSENS in the newspaper El Mundo

8 October, 2013 By a3p
PhD grants at the Centre for Telecommunications Studies (CETUC) of Rio de Janeiro

24 October, 2013 By a3p
The MCG works on the EU initiative METIS, which paves the way for the mobile and wireless communications system for 2020 & beyond

25 October, 2013 By a3p
Scientists at the Optical and the Quantum Communications Group (iTEAM-Universitat Politècnica de València) have collaborated on satellite OPTOS

7 December, 2013 By a3p

8G Building. 4th Floor, D access
Universitat Politècnica de València
Camino de Vera, s/n
46022 Valencia
SPAIN

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