Algorithms and architectures for advanced Forward Error Correction (FEC)
The objective of this research is the development of algorithms and architectures for hardware implementation of FEC blocks that will be required in future communications systems. We have focused in: Binary Low-Density Parity-Check codes decoders, Non-binary Low-Density Parity-Check codes decoders and Soft decoding of Reed-Solomon codes. We want to improve the operation of the LDPC decoders for high SNRs where the error-floor can appears. We have developed an FPGA-based hardware LDPC emulator to accelerate simulations for very low bit rates.