Publication

Efficient FPGA-Implementation of two's complement digit-serial/parallel multipliers

Year

2003

Authors

  Javier Valls Coquillat

Co-authors

J. Valls and E. Boemo

Journal

IEEE Transactions on Circuits and Systems II

Volume

50

Number

6

Pages

317-322

Dates

Junio

DOI

http://dx.doi.org/10.1109/TCSII.2003.811438

Research Groups

Digital Systems Integration Group (GISED)

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