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UPV
iTEAM
Grupo de Integración de Sistemas Digitales (GISED…

Grupo

Grupo de Integración de Sistemas Digitales (GISED)

Descripción	El grupo se centra en el diseño de algoritmos y arquitecturas de hardware orientadas para sistemas de comunicación digitales y procesamiento digital de señales basado en FPGA. Nuestras principales áreas de trabajo son: algoritmos y arquitecturas de avanzada Forward Error Correction (FEC), los sistemas basados en OFDM Comunicación Óptica, algoritmos y arquitecturas para radios de software basados en FPGA, DSP FPGA basado en ondas de ultrasonido, y la aritmética y de alto rendimiento DSP operadores para FPGA.
Website	www.gised.upv.es
Integrantes	Mª Asunción Pérez Pascual José Marín-Roig Ramón Javier Valls Coquillat Mª José Canet Subiela Pau Salvador Llàcer Trinidad Sansaloni Vicenç Almenar Terré Vicente Torres Carot
Líneas de Investigación	Algorithms and architectures for advanced Forward Error Correction (FEC) OFDM-based Optical CommunicationS Systems Algorithms and architectures for FPGA-based software radios FPGA-based DSP for ultrasound waves High performance arithmetic and DSP operators for FPGA
Areas de Investigación	Procesado de Señales
Proyectos de Investigación	Diseño de procesadores digitales de señal a medida Diseño eficiente de circuitos para telecomunicaciones en FPGA Diseño de cores-IP para redes inalámbricas basadas en OFDM. Optimización en área en la estación base. Hardware reconfigurable en sistemas de comunicaciones de banda ancha Implementación en FPGA de algoritmos para sistemas de comunicaciones inalámbricas de banda ancha. Algoritmos Avanzados de Corrección de Errores: ALCE Arquitecturas de FEC para sistemas de comunicaciones de muy alta velocidad Algoritmos y arquitecturas de FEC para futuros sistemas de comunicaciones Procesado Digital de Señales Ópticas en Medios Guiados Diseño e implementación en FPGA de un receptor para DSRC (Dedicated Short-Range Communications) Diseño detallado e implementación en FPGA de funciones del MODEM SS IOT (Spread Spectrum In Orbit Test) Diseño detallado e implementación en FPGA de un modem de alta velocidad Algoritmos de sincronización para MODEM DS-SS Desarrollo de tecnologías electrónicas Desarrollo de un core equalizador CMA
Laboratorios	Laboratorio de Comunicaciones digitales
Equipamiento	Instrumentación FPGA prototyping boards Software
Publicaciones	2016 Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm 2015 High-performance NB-LDPC decoder with reduction of message exchange Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser Reduction of complexity for Non-binary LDPC decoders with compressed messages Combined Data Detection Scheme for Zero-Padded OFDM Signals in MMF Links One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes 2014 Non-Binary LDPC Decoder Based on Simplified Enhanced Generalized Bit Flipping Algorithm Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree Multiple-Vote Symbol-Flipping Decoder for Non-Binary LDPC Codes Evaluation of optical ZP-OFDM transmission performance in multimode fiber links Non-Binary LDPC Decoder based on Symbol Flipping with Multiple Votes Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes with Low Error-Floor 2013 Multicore implementation of a fixed-complexity tree-search detector for MIMO communications Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes 2012 Serial Symbol-Reliability Based Algorithm For Decoding Non-Binary LDPC Codes Fully-parallel LUT-based (2048,1723) LDPC Code Decoder for FPGA High-Throughput FPGA-based Emulator for Structured LDPC Codes Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm On the Use of Graphic Processing Units for the Efficient Implementation of MIMO Detectors Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation Hardware Architecture of a Gaussian Noise Generator Based on Inversion Method FPGA implementation of an OFDM-based WLAN receiver Low complexity time synchronization algorithm for OFDM systems with repetitive preambles Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes 2011 High speed RS(255,239) decoder based on LCC decoding Practical aspects of preprocessing techniques for K-best tree search MIMO detectors Transmit diversity scheme for OFDM systems using the odd DFT Tridimensional block multiword LDPC decoding on GPUs Low cost Hardware Implementation of logarithm approximation 2010 An Evaluation of Precoding Techniques for Multiuser Communication Systems Extended LLL algorithm for efficient signal precoding in multiuser nication systems FPGA implementation of atan(Y/X) based on Logarithmic transformation and LUT-based techniques 2009 Recent advances in MIMO wireless systems 50 Years of CORDIC: Algorithms, Architectures and Applications Power consumption reduction in a Viterbi Decoder for OFDM-WLAN FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic Design and FPGA-implementation of a high performance timing recovery loop for broadband communications Low-power FPGA-implementation of atan(Y/X) using Look-Up Table methods for communication applications Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems 2008 Architectures for the implementation of a OFDM-WLAN Viterbi Decoder Efficient mapping of CORDIC Algorithm for OFDM-based WLAN 64-QAM 4x4 MIMO Decoders Based on Successive Projection Algorithm 2007 Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms Improvement of a Time Synchronization Algorithm for IEEE 802.11a/G WLAN Standard Time synchronization for the IEEE 802.11a/g WLAN Standard Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN FFT Spectrum Analyzer Project for Teaching Digital Signal Processing with FPGA devices Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs 2006 Design of high performance timing recovery loops for communication applications The use of CORDIC in Software Defined Radios: A tutorial Closed-form expression for the BER of m-QAM-OFDM systems over time and frequency-selective wireless channels 2005 Performance evaluation of fine time synchronizers for WLANs Efficient mapping on FPGA of a Viterbi decoder for wireless LANs Efficient FPGA implementation of CORDIC algorithm for circular and linear coordinates Statical power estimation for FPGAs Efficient pipeline FFT processors for WLAN MIMO-OFDM systems 2004 Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2 Design of a digital front-end transmitterfor OFDM-WLAN systems using FPGA A common FPGA-based synchronizer architecture for hiperlan 2 and IEEE 802.11A WLAN systems FPGA implementation of an IF transceiver for OFDM-based WLAN 2003 Digit-serial Complex-Number Multipliers on FPGAs Area-efficient FPGA-based FFT processor Efficient FPGA-Implementation of two's complement digit-serial/parallel multipliers Area-Optimized Implementation of Quadrature Direct Digital Frequency Synthesizers on LUT-based FPGAs 2002 Evaluation of CORDIC Algorithms for FPGA design 2001 Optimisation of direct digital frequency synthesizers based on CORDIC

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